Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

8.3. Pin Placement for Differential Channels

Each Intel® Agilex™ F-series and I-series GPIO sub-bank contains its own PLL. The PLL can drive all receiver and transmitter channels in the same sub-bank. However, the PLL of the sub-bank cannot drive receiver and transmitter channels in another GPIO sub-bank. You must use the dedicated clock pins to drive the LVDS PLLs.

Pins Arrangement in a GPIO Bank

In the device pin out files, the following pin index numbers indicate the location of the pins in a single GPIO bank:

  • 0 to 47bottom sub-bank
  • 48 to 95top sub-bank

PLLs Driving DPA-Enabled Differential Receiver Channels

  • For differential receivers, the PLL can drive all channels in the same I/O sub-bank but cannot drive across banks.
  • Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.
  • DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel® Quartus® Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.

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