6.1. LVDS SERDES Intel® FPGA IP Timing
|Source Synchronous Paths||
The source synchronous paths are paths where clock and data signals are passed from the transmitting devices to the receiving devices. For example:
|Dynamic Phase Alignment Paths||
A DPA block registers the I/O capture paths in soft-CDR and DPA-FIFO modes. The DPA block dynamically chooses the best phase from the PLL VCO clocks to latch the input data.
|Internal FPGA Paths||
The internal FPGA paths are the paths inside the FPGA fabric:
The Timing Analyzer reports the corresponding timing margins.
This .sdc file allows the Intel® Quartus® Prime Fitter to optimize timing margins with timing-driven compilation. The file also allows the Timing Analyzer to analyze the timing of your design.
The IP uses the .sdc for the following operations:
You can locate this file in the .qip generated during IP generation.
|sdc_util.tcl||This .tcl file is a library of functions and procedures that the .sdc uses.|
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