Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.1.5.2. LVDS SERDES Intel® FPGA IP PLL Settings

Table 13.  PLL Settings Tab
Parameter Value Description
Use external PLL
  • On
  • Off

Turn on to use an external PLL:

  • The IP does not instantiate a local PLL.
  • The IP creates a series of clock connections with the "ext" prefix. Connect these ports to an externally generated PLL.
  • For details about how to configure the external PLL, refer to the Clock Resource Summary tab of the parameter editor.

Default is Off.

This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration.

This option is disabled if you turn on Specify additional output clocks based on existing PLL.

Desired inclock frequency

Specifies the inclock frequency in MHz.

Default is 100.0.

Actual inclock frequency

Displays the closest inclock frequency to the desired frequency that can source the interface.

The displayed value changes according to the Desired inclock frequency parameter value.

FPGA/PLL speed grade

Displays the FPGA/PLL speed grade, which determines the operation range of the PLL.

The displayed value is based on the device selected in your project.

Enable pll_areset port

Exposes the pll_areset port. You can use the pll_areset signal to reset the entire LVDS interface.

This parameter is always turned on.

Core clock resource type

Specifies onto which clock network the IP core exports an internally generated coreclock.

The parameter is always set to Periphery.

Specify additional output clocks based on existing PLL
  • On
  • Off

Exports additional PLL output clocks based on the existing PLL settings.

You can only specify output clocks that are not currently used internally to the IP. The output clocks that are used internally are not modifiable.

Be careful when you set cross clock domain transfer with exported output clocks because these output clocks are asynchronous to other clocks generated by the IP.

The option is disabled if you turn on Use external PLL.

Table 14.  PLL Settings Tab—Output Clocks
Parameter Value Description
Number of Additional Clocks 0 to 4

Specifies the number of additional output clocks to expose.

Default is 0.

This option is available if you turn on Specify additional output clocks based on existing PLL.

Table 15.  PLL Settings Tab—outclkn The parameters in this table are available if the Number of Additional Clocks is 1 to 4. In this table, n represents the number of output clocks starting with 0. The parameter settings for outclk0 to outclk4 are reserved. The modifiable parameters for the output clocks start with outclk5 (pll_extra_clock0).
Parameter Value Description
Desired frequency 1.0 to 10000.0

Specifies the output clock frequency of the corresponding output clock port, pll_extra_clock[], in MHz.

Default is 100.0.

Actual frequency Depends on Desired frequency.

Allows you to select the actual output clock frequency from a list of achievable frequencies.

Default is the closest frequency achievable to Desired frequency.

Phase shift units ps

Specifies the phase shift unit for the corresponding output clock port, pll_extra_clockn , in picoseconds (ps).

Phase shift

Specifies the requested value for the phase shift.

The default is 0.0.

Actual phase shift Depends on Phase shift.

Allows you to select the actual phase shift from a list of achievable phase shift values.

The default is 0.0.

Desired duty cycle 0 to 100

Specifies the requested value for the duty cycle in percentage.

Actual duty cycle Depends on Desired duty cycle.

Allows you to select the actual duty cycle from a list of achievable duty cycle values in percentage.

Default is the closest duty cycle achievable to Desired duty cycle.

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