Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

4.3.2. DPA Mode

The DPA block selects the best possible dpa_fast_clock from the eight fast clock signals generated by the I/O PLL.

The receiver uses these serial clock signals for the following functions:

  • dpa_fast_clock— writing serial data into the synchronizer
  • fast_clock—reading serial data from the synchronizer, data realignment, and deserializer blocks

In DPA mode, the DPA FIFO synchronizes the retimed data to the high-speed SERDES clock domain. The DPA clock may shift the phase during the initial lock period. To avoid data run-through conditions caused by the FIFO write pointer creeping up to the read pointer, hold the FIFO in reset state until the DPA locks.

Figure 20. Receiver Data Path Block Diagram—DPA ModeIn this figure, all the receiver hardware blocks are active.


Note: In DPA mode, you must place all receiver channels of a SERDES instance in one I/O sub-bank. Because each I/O sub-bank has a maximum of 12 True Differential Signaling I/O buffer receiver pairs, each SERDES instance can support a maximum of 12 DPA receiver channels.

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