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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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4.3.2. DPA Mode
The DPA block selects the best possible dpa_fast_clock from the eight fast clock signals generated by the I/O PLL.
The receiver uses these serial clock signals for the following functions:
- dpa_fast_clock— writing serial data into the synchronizer
- fast_clock—reading serial data from the synchronizer, data realignment, and deserializer blocks
In DPA mode, the DPA FIFO synchronizes the retimed data to the high-speed SERDES clock domain. The DPA clock may shift the phase during the initial lock period. To avoid data run-through conditions caused by the FIFO write pointer creeping up to the read pointer, hold the FIFO in reset state until the DPA locks.
Figure 20. Receiver Data Path Block Diagram—DPA ModeIn this figure, all the receiver hardware blocks are active.
Note: In DPA mode, you must place all receiver channels of a SERDES instance in one I/O sub-bank. Because each I/O sub-bank has a maximum of 12 True Differential Signaling I/O buffer receiver pairs, each SERDES instance can support a maximum of 12 DPA receiver channels.