4.3.2. DPA Mode
The receiver uses these serial clock signals for the following functions:
- dpa_fast_clock— writing serial data into the synchronizer
- fast_clock—reading serial data from the synchronizer, data realignment, and deserializer blocks
In DPA mode, the DPA FIFO synchronizes the retimed data to the high-speed SERDES clock domain. The DPA clock may shift the phase during the initial lock period. To avoid data run-through conditions caused by the FIFO write pointer creeping up to the read pointer, hold the FIFO in reset state until the DPA locks.
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