Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
ID
721819
Date
9/05/2024
Public
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
3.4.1. Transmitter Output Clock Parameters Settings
You can refer to the Clock Resource Summary tab in the LVDS SERDES IP parameter editor for information about configuring and connecting an external PLL to the LVDS SERDES IP.
The Clock Resource Summary tab lists the required settings you need for the IOPLL Intel® FPGA IP:
- Frequencies, phase shifts, and duty cycles of the required clocks
- Instructions for connections and the compensation mode
You can specify the relationship of tx_outclock to the tx_out data using these parameters:
- Desired tx_outclock phase shift (degrees)
- Tx_outclock division factor
The parameters set the phase and frequency of the tx_outclock based on the fast_clock, which operates at the serial data rate. You can set the tx_outclock frequency by selecting the available division factors.
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