Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
ID
721819
Date
9/05/2024
Public
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
5.1.5.4. LVDS SERDES Intel® FPGA IP Transmitter Settings
The parameter options in the Transmitter Settings tab are available if you select the TX functional mode in the General Settings tab.
Parameter | Value | Description |
---|---|---|
Enable tx_coreclock port |
|
Turn on to expose the tx_coreclock port that you can use to drive the core logic feeding the transmitter. Default is On. Intel recommends that you use the tx_coreclock output signal if it is requested.
Note: This option is disabled if the Use external PLL option in the PLL Settings tab is turned on. To expose the tx_coreclock when using external PLL, turn off Use external PLL option before turning on the Enable tx_coreclock port. After making changes to Enable tx_coreclock port, you can turn Use external PLL back on.
|
Enable tx_outclock port |
|
Turn on to expose the tx_outclock port. Default is On.
Turning on this parameter reduces the maximum number of channels per transmitter interface by one channel. |
Desired tx_outclock phase shift (degrees) |
|
Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock. Default is 0. |
Actual tx_outclock phase shift (degrees) | Depends on the Desired tx_outclock phase shift (degrees) input. Refer to related information. |
Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift. |
Tx_outclock division factor | Depends on the SERDES factor. | Specifies the ratio of the fast clock frequency to the outclock frequency. For example, the maximum number of serial transitions per outclock cycle. |
Related Information