Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

7.10. Modules for Clocked Video Input II IP Core

The architecture for the Clocked Video Input II IP differs from the previous clocked video input IP.
Figure 42. Block Diagram for Clocked Video Input II IPThe figure shows a block diagram of the Clocked Video Input II IP architecture.
Table 21.  Modules for Clocked Video Input II IPThe table below describes the modules in the Clocked Video Input II IP architecture.
Modules Description
Sync_conditioner
  • In embedded sync mode, this module extracts the embedded syncs from the video data and produces h_sync, v_sync, de, and f signals.
  • The module also extracts any ancillary packets from the video and writes them into a RAM in the control module.
  • In separate sync modes, this module converts the incoming sync signals to active high and produces h_sync, v_sync, de, and f signals.
  • If you turn on the Extract field signal parameter, the f signal is generated based on the position of the V-sync. If the rising edge of the V-sync occurs when h_sync is high, the f signal is set to 1, otherwise it is set to 0.
Resolution_detection
  • This module uses the h_sync, v_sync, de, and f signals to detect the resolution of the incoming video.
  • The resolution consists of:
    • width of the line
    • width of the active picture region of the line (in samples)
    • height of the frame (or fields in the case of interlaced video)
    • height of the active picture region of the frame or fields (in lines)
    The IP writes the resolutions into a RAM in the control module.
  • The resolution detection module also produces some additional information.
  • It detects whether the video is interlaced by looking at the f signal. It detects whether the video is stable by comparing the length of the lines. If two outputs of the last three lines have the same length. the video is considered stable.
  • Finally, it determines if the resolution of the video is valid by checking that the width and height of the various regions of the frame has not changed.
Write_buffer_fifo
  • This module writes the active picture data, marked by the de signal, into a FIFO that is used to cross over into the is_clk clock domain.
  • If you set the Color plane transmission format parameter to Parallel for the output, the write_buffer_fifo also converts any incoming sequential video, marked by the hd_sdn signal, into parallel video before writing it into the FIFO buffer.
  • The Go bit of the Control register must be 1 on the falling edge of the v_sync signal before the write_buffer_fifo module starts writing data into the FIFO buffer.
  • If an overflow occurs because of insufficient room in the FIFO buffer, the module stops writing active picture data into the FIFO buffer.
  • It waits for the start of the next frame before attempting to write in video data again.
Control
  • This module provides the register file that is used to control the IP through an Avalon memory-mapped target interface.
  • It also holds the RAM that contains the detected resolution of the incoming video and the extracted auxiliary packet which is read by the av_st_output module, to form the control packets, and can also be read from the Avalon memory-mapped target interface.
  • The RAM provides the clock crossing between the vid_clk and is_clk clock domains.
Av_st_output
  • This module creates the control packets, from the detected resolution read from the control module, and the video packets, from the active picture data read from the write_buffer_fifo module.
  • The IP sends the packets to the Video Output Bridge which turns them into Avalon streaming video packets.
Sdi_resampler
  • This module is present only when you turn on the Support 6G and 12G-SDI parameter in the parameter editor.
  • It reformats the video stream from 2SI 6G- and 12G-SDI formats into the Avalon streaming video raster format and reformats the video stream from 3G-, HD-, and SD-SDI formats into the Avalon streaming video format.
    Note: This module reformats the SDI video streams only for configurations with 4 pixels in parallel.