Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
Document Table of Contents Zero-Delay Buffer Mode

In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. This mode is only supported for I/O bank I/O PLL.

In this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock input or output pins.

To ensure phase alignment between the clk pin and the external clock output (CLKOUT) pin in ZDB mode, instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path connecting the fbout and fbin ports of the PLL. The bidirectional I/O pin must always be assigned a single-ended I/O standard, and must not be globally promoted. The PLL uses this bidirectional I/O pin to mimic and compensate for the output delay from the clock output port of the PLL to the external clock output pin.

Note: To avoid signal reflection when using ZDB mode, do not place board traces on the bidirectional I/O pin.
Figure 15. Example of Phase Relationship Between the PLL Clocks in ZDB Mode

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