Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
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2.1.1.3. Programmable Clock Routing

The Intel® Quartus® Prime software automatically configures the clock switch multiplexer, clock tap multiplexer, SCLK multiplexer, and row clock multiplexers to generate skew-balanced clock trees. The resulting routing path distributes the signal from the clock source to all target destinations in one or more clock sectors.

The Intel® Quartus® Prime software creates efficiently balanced clock trees of various sizes, ranging from a single clock sector to the entire device, as shown in the following figure. By default, the Intel® Quartus® Prime software automatically determines the size and location of the clock tree. Alternatively, you can directly constrain the clock tree size and location by using either a Clock Region Assignment or Logic Lock Regions.

The total insertion delay for the clock network depends on the number of clock resources needed to implement the clock tree, increasing with the distance of the furthest clock destination from the signal source. As delay increases, the worst-case skew for crossing clock networks using different clock tree branches grows, potentially degrading the maximum performance. For very high-speed clock signals, it is advantageous to follow these guidelines:

  • Reduce the number of clock networks driven, which reduces the clock skew.
  • Reduce the distance between the clock source and the furthest destination, which reduces both clock skew and total clock insertion delay.
Figure 4. Examples of Clock Networks Sizes Using Intel® Agilex™ Device Programmable Clock Routing

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