Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 11/09/2022

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Document Table of Contents

2.1.1. Clock Network Architecture

Each Intel® Agilex™ device is divided into a number of evenly sized clock sectors.

Figure 1. Clock Sector Floorplan for Intel® Agilex™ DevicesThis figure shows an example of the clock sectors in an Intel® Agilex™ device, which is implemented as an array of sectors—5 rows and 6 columns in this example. I/O banks are at the top and bottom of the Intel® Agilex™ device.