Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
Document Table of Contents

2.2.2. PLL Usage

I/O bank I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use both the I/O bank I/O PLLs and fabric-feeding I/O PLLs to:

  • Reduce the number of required oscillators on the board
  • Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
  • Simplify the design of external memory interfaces and high-speed LVDS interfaces
  • Ease timing closure because the I/O PLLs are tightly coupled with the I/Os
  • Compensate for clock network delay
  • Zero delay buffering

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