Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
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5.4.3. IOPLL IP Core Parameters - Cascading Tab

Table 10.   IOPLL IP Core Parameters - Cascading Tab
Parameter Value Description
Connect to an upstream PLL through Core clock Network Cascading (create a permit_cal input signal) On or Off Turn on to create an input port to enable destination (downstream) PLL power-up calibration. Connect source (upstream) PLL locked signal to this input port.
Create a ‘cascade out’ signal to connect with a downstream PLL 12 On or Off Turn on to create the cascade_out port, which indicates that this PLL is a source and connects with a destination (downstream) PLL.
cascade_out source 12 06 Specifies which output clock to be used as cascading source.
Create an adjpllin or cclk signal to connect with an upstream PLL 12 On or Off Turn on to create an input port, which indicates that this PLL is a destination and connects with a source (upstream) PLL.
12 This option is only available when selecting I/O Bank on the IOPLL Type.

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