Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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2.1.3.2. Clock Divider

There is one clock divider per I/O bank and transceiver bank. The clock divider is a part of the periphery DCM block and is located close to the root clock gate. The outputs of the clock divider cannot be gated by the root clock gate in the same periphery DCM block. However, this limitation does not apply to the SCLK gate. The clock divider output in the periphery DCM block can drive a SCLK gate after going through the programmable clock routing.

The clock divider has three outputs as follows:

  • First output—passes through the input clock.
  • Second output—divides the input clock by two.
  • Third output—divides the input clock by four.

These three clock outputs are edge-aligned at the output of the clock divider.

Figure 7. Clock Divider Timing Diagram

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