Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
Document Table of Contents LAB Clock Gate

The Intel® Agilex™ LAB register has built-in clock gating functionality. The register clock enable mechanism is a hardened data feedback, as shown in the Clock Gating and Clock Divider in Intel® Agilex™ Clock Network diagram. The LAB clock gate offers no associated power savings because this is a purely functional clock enable.

The Intel® Quartus® Prime Analysis & Synthesis stage of the Compiler infers a LAB clock gate from a behavioral description of clock gating in the register transfer level (RTL). If you want a physical clock gate, you must instantiate it explicitly.

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