Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
Document Table of Contents

2.1.3.1.1. Root Clock Gate

There is one root clock gate per I/O bank and transceiver bank. This gate is a part of the periphery DCM.

The Intel® Agilex™ root clock gate is intended for limited clock gating scenarios where high insertion delay can be tolerated. When you use a root clock gate, set multicycle of several clock cycles between the generation of the clock gating signal in the core and the gated clock in the periphery to meet the timing requirement. For high frequency clocks that require single-cycle gating, use sector clock gates.

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