1. Intel® Agilex™ Clocking and PLL Overview 2. Intel® Agilex™ Clocking and PLL Architecture and Features 3. Intel® Agilex™ Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. IOPLL Reconfig Intel® FPGA IP Core 7. Intel® Agilex™ Clocking and PLL User Guide Archives 8. Document Revision History for the Intel® Agilex™ Clocking and PLL User Guide
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Guidelines: I/O PLL Reconfiguration 3.6. Clocking Constraints 3.7. IP Core Constraints 3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP 6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 6.3. IOPLL Reconfig IP Core Reconfiguration Modes 6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core 6.5. Address Bus and Data Bus Settings 6.6. Design Example
3.1. Guidelines: Clock Switchover
When implementing clock switchover in Intel® Agilex™ I/O PLLs, refer to the following guidelines:
- Automatic clock switchover requires that the inclk0 and inclk1 frequencies are within 20% of each other. Failing to meet this requirement causes the clkbad0 and clkbad1 signals to not function properly.
- When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2×). However, differences in frequency, phase, or both, of the two clock sources may cause the I/O PLL to lose lock. Resetting the I/O PLL ensures that you maintain the correct phase relationships between the input and output clocks.
- Both inclk0 and inclk1 must be running when the extswitch signal goes low to initiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
- Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth I/O PLL. When referencing input clock changes, the low-bandwidth I/O PLL reacts more slowly than a high-bandwidth I/O PLL. When switchover happens, a low-bandwidth I/O PLL propagates the stopping of the clock to the output more slowly than a high-bandwidth I/O PLL. However, the low-bandwidth I/O PLL also increases lock time.
- After a switchover occurs, there may be a finite resynchronization period for the I/O PLL to lock onto a new clock. The time it takes for the I/O PLL to relock depends on the I/O PLL configuration.
- If the phase relationship between the input clock to the I/O PLL and the output clock from the I/O PLL is important in your design, assert the reset signal for at least 10 ns after performing a clock switchover. Wait for the locked signal to go high and be stable before re-enabling the output clocks from the I/O PLL.
- The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO locks on to the backup clock, as shown in the following figure.
Figure 24. VCO Switchover Operating Frequency
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