Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
Document Table of Contents

5.3.1. Generating a New IP-XACT File

To generate a new IP-XACT file, follow these steps:

  1. On the IOPLL Intel FPGA IP dialog box, click Generate HDL.
  2. Ensure either Verilog or VHDL is selected for the Create HDL design files for synthesis option. Click Generate to generate the IP-XACT file.
The following IP-XACT files are generated:
  • agilex_iobank_pll.ipxact file—When IOPLL Type is I/O Bank
  • agilex_fabric_pll.ipxact file—When IOPLL Type is Fabric-Feeding

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