Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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2.2.4. PLL Architecture

Figure 9. I/O Bank I/O PLL High-Level Block Diagram for Intel® Agilex™ Devices
Figure 10. Fabric-Feeding I/O PLL High-Level Block Diagram for Intel® Agilex™ Devices
Note: The dedicated clock inputs can feed only one PLL via the dedicated clock path. To feed the second PLL, the clock must be routed onto a global clock network.

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