Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
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8. Document Revision History for the Intel® Agilex™ Clocking and PLL User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.03.26 20.3 Updated the gated and ungated data bus bit setting (binary) in the Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration table.
2021.12.13 20.3 Updated the connection for the dedicated clock inputs in the Fabric-Feeding I/O PLL High-Level Block Diagram for Intel® Agilex™ Devices diagram.
2021.09.21 20.3
  • Updated the description in the Root Clock Gate section.
  • Added a note in the PLL Architecture section.
  • Added description on PLL loses lock in the Locked section.
  • Updated the Manual Switchover mode description for the Switchover Mode parameter in the IOPLL IP Core Parameters - Settings Tab for Intel® Agilex™ Devices table.
  • Updated the address for C1 to C7 counters in the Address Bus and Data Bus Settings for Advanced Mode Reconfiguration table.
  • Updated data[7:4] for C1 to C7 counters in the Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core table.
  • Updated mgmt_writedata[7..0] signal in the Waveform Example for Advanced Mode Reconfiguration Design Example diagram.
  • Updated mgmt_writedata[7..0] signal in the Waveform Example for Clock Gating Reconfiguration Design Example diagram.
2021.06.21 20.3 Updated the PLL Locations section.
2021.03.29 20.3
  • Added table: Spread-Spectrum Input Clocking Supported Profile.
  • Added guideline: Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP .
  • Updated the IOPLL Reconfig Intel® FPGA IP Core Current Release Information table.
2020.09.28 20.3
  • Updated the note to the spread-spectrum input clock tracking feature in the PLL Features in Intel® Agilex™ Devices table.
  • Added the IP-XACT File Generation section under IOPLL Intel® FPGA IP Core.
  • Updated the Charge Pump Setting [2:0] value for Multiple Factor 141–160 in the Fabric-Feeding I/O PLL Data Bus Setting for Bandwidth Control and Charge Pump (For High Bandwidth) table.
  • Updated the high bandwidth ripplecap setting for Multiply Factor 141–160 in the Fabric-Feeding I/O PLL Data Bus Setting for Ripplecap table.
  • Updated C counters in the following sections:
    • I/O Bank I/O PLL High-Level Block Diagram for Intel® Agilex™ Devices
    • Fabric-Feeding I/O PLL High-Level Block Diagram for Intel® Agilex™ Devices
    • Address Bus and Data Bus Settings for Advanced Mode Reconfiguration table
    • Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration table
    • Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core table
2020.04.13 20.1
  • Updated the Examples of Clock Networks Sizes Using Intel® Agilex™ Programmable Clock Routing diagram.
  • Removed zero-delay buffer compensation support for fabric-feeding I/O PLL in the following sections:
    • PLL Features in Intel® Agilex™ Devices table
    • Fabric-Feeding I/O PLL High-Level Block Diagram for Intel® Agilex™ Devices diagram
  • Added description for top and bottom sub-banks in the PLL Locations section. Updated the I/O PLL Locations in I/O Bank diagram.
  • Updated the Zero-Delay Buffer Mode section.
    • Mentioned that the ZDB mode is only supported for I/O bank I/O PLL.
    • Added description about the bidirectional I/O pin must not be globally promoted.
  • Added information on IOPLL Reconfig IP ports in the PLL Reconfiguration and Dynamic Phase Shift section. Moved the information from the IOPLL Reconfig Intel® FPGA IP Core section.
  • Added a note to zero delay buffer for Compensation Mode in the IOPLL IP Core Parameters - PLL Tab for Intel® Agilex™ Devices table.
  • Added description on supported output clocks and C counters in the IOPLL IP Core Parameters - Advanced Parameters Tab for Intel® Agilex™ Devices table.
  • Added a design example with three reconfiguration options using IOPLL Reconfig Intel® FPGA IP core.
2019.12.18 19.3 Removed scanclk signal in the Guideline: I/O PLL Reconfiguration section.
2019.10.31 19.3
  • Added the Examples of Clock Networks Sizes Using Intel® Agilex™ Programmable Clock Routing diagram in the Programmable Clock Routing section.
  • Updated the number of resources available in the Programmable Clock Routing Resources for Intel® Agilex™ Devices table.
  • Updated the PLL Features in Intel® Agilex™ Devices table.
    • Updated C counter divide factor range from '1 to 510' to '1 to 512'.
    • Added a note to dedicated external clock outputs.
    • Removed the following PLL features for fabric-feeding I/O PLL.
      • Dedicated external clock outputs
      • External feedback input pin
      • External feedback compensation
    • Added spread-spectrum input clock tracking feature.
  • Updated the PLL Usage section.
  • Removed external feedback mode in the Fabric-Feeding I/O PLL High-Level Block Diagram for Intel® Agilex™ Devices diagram.
  • Clarified that EFB mode is only supported for I/O bank I/O PLL.
  • Updated the PLL Cascading section.
    • Added description that Intel® Agilex™ devices does not support I/O PLL cascading within the same I/O bank.
    • Updated outclk[8:0] to outclk[6:0] in the I/O-PLL-to-I/O-PLL cascading diagrams.
  • Added the following guidelines:
    • Guideline: I/O PLL Reconfiguration
    • Clocking Constraints
    • IP Core Constraints
  • Added information for the following IP cores:
    • Clock Control Intel® FPGA IP version 1.0.0
    • IOPLL Intel® FPGA IP version 19.3.0
    • IOPLL Reconfig Intel® FPGA IP version 19.3.0
2019.04.02 Initial release.

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