Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 11/09/2022

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Document Table of Contents

4.3. Clock Control IP Core Ports and Signals

Table 6.   Clock Control IP Core Ports for Intel® Agilex™ Devices
Port Name Description
inclk Input signal to the clock network.
inclk0x, inclk1x, inclk2x, inclk3x Input signals to the clock network based on the value selected for the Number of Clock Inputs parameter.

Input that dynamically selects the clock source to drive the clock network that is driven by the clock buffer.

Input port [1 DOWNTO 0] wide.

The following list shows the signal selection for the clkselect[] value:

  • 2’b00 selects inclk0x
  • 2’b01 selects inclk1x
  • 2’b10 selects inclk2x
  • 2’b11 selects inclk3x
outclk Output of the Clock Control IP core when Clock Divider option is not selected.
ena Clock enable of the clock gate block. This signal is active-high.
clock_div1x, clock_div2x, clock_div4x Outputs of the Clock Control IP core when the Clock Divider option is selected. The exact combination of ports exposed depends on the value specified for the Clock Divider Output Ports parameter.
  • clock_div1x is the same as inclk
  • clock_div2x divides inclk by 2
  • clock_div4x divides inclk by 4