4.3. Clock Control IP Core Ports and Signals
|inclk||Input signal to the clock network.|
|inclk0x, inclk1x, inclk2x, inclk3x||Input signals to the clock network based on the value selected for the Number of Clock Inputs parameter.|
Input that dynamically selects the clock source to drive the clock network that is driven by the clock buffer.
Input port [1 DOWNTO 0] wide.
The following list shows the signal selection for the clkselect value:
|outclk||Output of the Clock Control IP core when Clock Divider option is not selected.|
|ena||Clock enable of the clock gate block. This signal is active-high.|
|clock_div1x, clock_div2x, clock_div4x||Outputs of the Clock Control IP core when the Clock Divider option is selected. The exact combination of ports exposed depends on the value specified for the Clock Divider Output Ports parameter.
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