Intel® Agilex™ Clocking and PLL User Guide

Download
ID 683761
Date 3/26/2022
Public
Document Table of Contents

2.1.2. Clock Resources

Table 1.  Programmable Clock Routing Resources for Intel® Agilex™ Devices
Number of Resources Available Source of Clock Resource
32 pairs of unidirectional programmable clock routing at the boundary of each clock sector

For transceiver bank:

  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • REFCLK pins
  • Core signals 1

For I/O bank:

  • I/O PLL C counter outputs
  • I/O PLL M counter outputs for feedback
  • Phase aligner counter outputs
  • Dynamic phase alignment (DPA) clock output
  • Clock input pins
  • Core signals 1

For more information about the clock input pins connections, refer to the pin connection guidelines.

1 Core signals drive directly to programmable clock routing through clock switch multiplexers in the clock sectors instead of the periphery DCM block.

Did you find the information on this page useful?

Characters remaining:

Feedback Message