Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
Document Table of Contents

2.2.9. Programmable Duty Cycle

The programmable duty cycle feature allows I/O PLLs to generate clock outputs with a variable duty cycle. This feature is only supported by the I/O PLL post-scale counters, C.

The I/O PLL C counter value determines the precision of the duty cycle. The precision is 50% divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty-cycle options from 5% to 90%. If the I/O PLL is in external feedback mode, set the duty cycle for the counter driving the fbin pin to 50%.

The Intel® Quartus® Prime software automatically adjusts the VCO frequency according to the required duty cycle that you enter in the IP core.

Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks.

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