Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 11/09/2022

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Document Table of Contents

2.2.1. PLL Features

Table 2.  PLL Features in Intel® Agilex™ Devices—Preliminary
Feature I/O Bank I/O PLL Fabric-Feeding I/O PLL
Integer PLL Yes Yes
Number of C output counter 7 3
M counter divide factor range 4 to 160 4 to 160
N counter divide factor range 1 to 110 1 to 110
C counter divide factor range 1 to 512 1 to 512
Dedicated external clock outputs 2 Yes
Dedicated clock input pins Yes Yes
External feedback input pin Yes
Source synchronous compensation 3 Yes Yes
Direct compensation Yes Yes
Normal compensation 3 Yes Yes
Zero-delay buffer compensation Yes
External feedback compensation Yes
LVDS compensation Yes
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes
Phase shift resolution 4 78.125 ps 78.125 ps
Programmable duty cycle Yes Yes
Power down mode Yes Yes
Bandwidth setting Low, medium, and high Medium and high
Spread-spectrum input clock tracking 5 Yes Yes
Table 3.  Spread-Spectrum Input Clocking Supported Profile
Spread-Spectrum Clocking Parameter Setting
Modulation frequency 200 kHz
Center or down spread Down spread
Frequency deviation ±1%
Modulation profile Triangle
2 For dedicated external clock outputs, you must enable access to external clock output port through IOPLL Intel® FPGA IP core. There are 2 dedicated external clock output available for each I/O bank I/O PLL.
3 Non-dedicated feedback path option is available for this compensation mode.
4 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Intel® Agilex™ device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
5 Provided that input clock jitter is within the input jitter tolerance specifications. Intel recommends that the spread-spectrum support profile is down spread, ±0.5% and Fmod = 200 kHz.