Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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2.2.6. PLL Feedback Modes

PLL feedback modes compensate for clock network delays to align the rising edge of the output clock with the rising edge of the PLL's reference clock. Select the appropriate type of compensation for the timing critical clock path in your design.

PLL compensation is not always needed. Configure a PLL in direct (no compensation) mode unless you need compensation. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.

The default PLL feedback mode is direct compensation mode.

I/O PLLs support the following PLL feedback modes:

  • Direct compensation
  • LVDS compensation
  • Source synchronous compensation
  • Normal compensation
  • Zero delay buffer (ZDB) compensation
  • External feedback (EFB) compensation

Normal and source synchronous compensation modes compensate for the insertion delay of a routed core clock. For Intel® Agilex™ devices, you can achieve core clock compensation by routing a dedicated feedback clock from the M counter in the I/O PLL to emulate the insertion delay of the compensated C counter output clock network.

Intel recommends the non-dedicated feedback mechanism because it uses the clock resources most efficiently.

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