Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
Document Table of Contents

1.2. PLLs Overview

Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Intel® Agilex™ device family contains the following I/O PLLs for core applications. The I/O PLLs can only function as integer PLLs.

  • Fabric-feeding I/O PLLs—three C counter outputs available and do not support PLL cascading
  • I/O bank I/O PLLs—seven C counter outputs available and support PLL cascading

The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains two I/O bank I/O PLLs and one fabric-feeding I/O PLL.

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