Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 11/09/2022

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Document Table of Contents

1.2. PLLs Overview

Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Intel® Agilex™ device family contains the following I/O PLLs for core applications. The I/O PLLs can only function as integer PLLs.

The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains two I/O bank I/O PLLs and one fabric-feeding I/O PLL.