Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
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6.6.2. Reconfiguration Option: Advanced Mode Reconfiguration and Recalibration Using IOPLL Reconfig IP Core

After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration at medium bandwidth:

  • 400 MHz with 0 ps phase shift on counter C1 output
  • 200 MHz with 0 ps phase shift on counter C2 output

The state machine initiates the I/O PLL recalibration process when the I/O PLL reconfiguration operation is complete.

To run the design example using advanced mode reconfiguration, perform these steps:

  1. Open AN.stp file and program the device top.sof.
  2. In the In-System Sources & Probes IP core, assert mode_0 to high pulse and mode_1 remains low.
  3. Assert a high pulse on the mgmt_reset signal to reset the IOPLL Reconfig IP core.
  4. Assert a high pulse on the reset_SM signal to start the I/O PLL reconfiguration operation.
Figure 27. Waveform Example for Advanced Mode Reconfiguration Design Example

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