Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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2.2.3. PLL Locations

Figure 8. I/O PLL Locations in I/O Bank

Within an I/O bank, the top sub-bank is placed near the edge of the die, while the bottom sub-bank is placed near the FPGA core.

If one of the sub-banks is not available in the I/O bank, the dedicated clock input and clock output pins for the I/O PLL located in this unbonded sub-bank are unavailable. However, you can still use the I/O PLL in the following scenarios by ensuring the VCCPT is powered up:

  • PLL cascading and reconfiguration are supported.
  • You may use any available regular I/O pins as clock input and clock output pins for this I/O bank I/O PLL.

If one of the sub-banks is not available in the I/O bank, the fabric-feeding I/O PLL in this I/O bank has only one pair of dedicated clock input pins which is from the available sub-bank. Reconfiguration is supported by this fabric-feeding I/O PLL.

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