Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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6.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores

To connect the IOPLL and IOPLL Reconfig IP cores in your design, follow these steps:

  1. Connect the reconfig_to_pll[29..0] bus on the IOPLL Reconfig IP core to the reconfig_to_pll[29..0] bus on the IOPLL IP core.
  2. Connect the reconfig_from_pll[10..0] bus on the IOPLL Reconfig IP core to the reconfig_from_pll[10..0] bus on the IOPLL IP core.
  3. Connect the mgmt_clk port to a valid clock source.
  4. Connect the mgmt_reset port, mgmt_waitrequest port, mgmt_read port, mgmt_write port, mgmt_readdata[7..0] bus, mgmt_writedata[7..0] bus, and mgmt_address[9..0] bus to user control logic to perform read and write operations.

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