5.5. IOPLL IP Core Ports and Signals
|refclk||Input||Required||The reference clock source that drives the I/O PLL.|
|rst||Input||Required||The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0.|
The external feedback input port for the I/O PLL.
The IOPLL IP core creates this port when the I/O PLL is operating in external feedback mode or zero-delay buffer mode. To complete the feedback loop, a board-level connection must connect the fbclk port and the external clock output port of the I/O PLL.
The port that feeds the fbclk port through the mimic circuitry.
The fboutclk port is available only if the I/O PLL is in external feedback mode.
The bidirectional port that connects to the mimic circuitry. This port must connect to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL.
The zdbfbclk port is available only if the I/O PLL is in zero-delay buffer mode.
|locked||Output||Optional||The IOPLL IP core drives this port high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock.|
|refclk1||Input||Optional||Second reference clock source that drives the I/O PLL for clock switchover feature.|
|extswitch||Input||Optional||Active low signal. Assert the extswitch signal low (1’b0) for at least three clock cycles to manually switch the clock.|
|activeclk||Output||Optional||Output signal to indicate which reference clock source is in used by I/O PLL.|
|clkbad||Output||Optional||Output signal that indicates the status of reference clock source is good or bad.|
|cascade_out||Output||Optional||Output signal that feeds into downstream I/O PLL.|
|adjpllin||Input||Optional||Input signal that feeds from upstream I/O PLL.|
|outclk_||Output||Optional||Output clock from I/O PLL.|
|permit_cal||Input||Optional||This is an input port for the downstream I/O PLL. Connect this permit_cal port to the locked output port of the upstream I/O PLL. Connecting this permit_cal port ensures that the cascaded I/O PLLs are calibrated in the correct order.|
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