Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
Document Table of Contents

2.2.12. PLL Reconfiguration and Dynamic Phase Shift

There are two I/O bank I/O PLLs inside an I/O bank, one located at the top sub-bank and the other located at the bottom sub-bank. The two I/O bank I/O PLLs share the same IOPLL Reconfig IP ports in the I/O bank. Thus, only the I/O bank I/O PLL located in the top sub-bank can be implemented for PLL reconfiguration and dynamic phase shift. The fabric-feeding I/O PLL has its own IOPLL Reconfig IP ports and can always be reconfigured.

Intel® Agilex™ devices support PLL reconfiguration and dynamic phase shift with the following features:

  • PLL reconfiguration—I/O PLL can reconfigure the M, N, C counters, and bandwidth setting.
  • Dynamic phase shift—I/O PLL can perform positive or negative phase shift. Able to shift multiple phase steps each time, where one phase step is equal to 1/8 of the VCO period.

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