Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
Document Table of Contents

3.4. Guidelines: Configuration Constraints

The I/O PLL configuration must obey the following constraints:

  • The phase frequency detector (PFD) and VCO each have a legal frequency range of operation.
  • The loop filter settings must be appropriate for the M counter value and user-selected bandwidth mode.

If any of these configuration constraints are violated, the I/O PLL may fail to lock or may exhibit poor jitter performance.

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