Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
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5.4.5. IOPLL IP Core Parameters - Advanced Parameters Tab

Table 12.   IOPLL IP Core Parameters - Advanced Parameters Tab for Intel® Agilex™ Devices
Parameter Value Description
Advanced Parameters Displays a table of physical PLL settings that are implemented based on your input.

I/O bank I/O PLL supports a maximum of 7 output clocks. The IOPLL IP core implements the output clocks using C1 to C7 counters.

Fabric-feeding I/O PLL supports a maximum of 3 output clocks. The IOPLL IP core implements the output clocks using C1 to C3 counters.

Table 13.  Output Clocks and C Counters Mapping
Output Clock C Counter
outclk0 C1
outclk1 C2
outclk2 C3
outclk3 C4
outclk4 C5
outclk5 C6
outclk6 C7

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