Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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2.2.10. PLL Cascading

Intel® Agilex™ devices support PLL-to-PLL cascading. You can cascade a maximum of two PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL.

If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting, and the destination (downstream) PLL must have a high-bandwidth setting for I/O PLL. During cascading, the output of the source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the cascaded PLLs may amplify phase noise at certain frequencies. Intel® Agilex™ devices do not support I/O PLL cascading within the same I/O bank.

Intel® Agilex™ devices support the following PLL-to-PLL cascading modes for I/O bank I/O PLL:

  • I/O-PLL-to-I/O-PLL cascading via dedicated cascade path—upstream I/O PLL and downstream I/O PLL must be in the same I/O column.
  • I/O-PLL-to-I/O-PLL cascading via core clock fabric—no restriction on locations of upstream and downstream I/O PLL.

The permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes.

The following figures show the connectivity required between the upstream and downstream I/O PLL for both the PLL cascading modes.

Figure 17. I/O-PLL-to-I/O-PLL Cascading Via Dedicated Cascade Path
Figure 18. I/O-PLL-to-I/O-PLL Cascading Via Core Clock Fabric

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