Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core

Table 17.   Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core for Intel® Agilex™ Devices
Port Direction Description
mgmt_clk Input Dynamic reconfiguration clock that drives the IOPLL Reconfig IP core. The maximum input clock frequency is 100 MHz. This clock can be an independent clock source. It must be free running, which means it cannot be connected to the output of the I/O PLL being reconfigured.
mgmt_reset Input Active high signal. Synchronous reset input to clear all the data in the IOPLL Reconfig IP core.
mgmt_waitrequest Output This port goes high when PLL reconfiguration process started and remains high during PLL reconfiguration. After PLL reconfiguration process completed, this port goes low.
mgmt_write Input Active high signal. Asserts to indicate a write operation.
mgmt_read Input Active high signal. Asserts to indicate a read operation.
mgmt_writedata[7..0] Input Writes data to this port when mgmt_write signal is asserted.
mgmt_readdata[7..0] Output Reads data from this port when mgmt_read signal is asserted.
mgmt_address[9..0] Input Specifies the address of the data bus for a read or write operation.
reconfig_from_pll[10..0] Input Bus that connects to reconfig_from_pll[10..0] bus in the IOPLL Intel® FPGA IP core.
reconfig_to_pll[29..0] Output Bus that connects to reconfig_to_pll[29..0] bus in the IOPLL IP core.

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