Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
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6.5.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration

Table 26.  Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration
Output Clock Data Bus Bit Setting (Binary)
C1 data[0]

Gated = 1'b1

Ungated = 1'b0

C2 data[1]
C3 data[2]
C4 data[3]
C5 data[4]
C6 data[5]
C7 data[6]

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