Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 3/26/2022
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2.2.6.3. Source Synchronous Compensation Mode

If the data and clock signals arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Only one output clock can be compensated in source synchronous compensation mode.

Intel recommends source synchronous mode for source synchronous data transfers.

Figure 13. Example of Phase Relationship Between Clock and Data in Source Synchronous Mode


The source synchronous mode compensates for the delay of the clock network used and any difference in the delay between the following two paths:

  • Data pin to the IOE register input
  • Clock input pin to the PLL PFD input

The Intel® Agilex™ PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode.

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