1. Intel® Agilex™ Clocking and PLL Overview 2. Intel® Agilex™ Clocking and PLL Architecture and Features 3. Intel® Agilex™ Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. IOPLL Reconfig Intel® FPGA IP Core 7. Intel® Agilex™ Clocking and PLL User Guide Archives 8. Document Revision History for the Intel® Agilex™ Clocking and PLL User Guide
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Guidelines: I/O PLL Reconfiguration 3.6. Clocking Constraints 3.7. IP Core Constraints 3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP 6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 6.3. IOPLL Reconfig IP Core Reconfiguration Modes 6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core 6.5. Address Bus and Data Bus Settings 6.6. Design Example
3.3. Guidelines: Resetting the PLL
To reset the PLL, refer to the following guidelines:
- When changing the M counter, N counter, or loop filter settings, the I/O PLL may lose and regain lock. To maintain the appropriate phase relationship between the reference clock and output clocks, assert the areset signal to reset the I/O PLL after reconfiguration is complete. Intel recommends always resetting the I/O PLL after any reconfiguration operation to the M counter, N counter, or loop filter settings.
- When changing the C counter settings, you may lose the expected phase relationship between the C counters. Assert the areset signal after reconfiguration is complete to restore the expected phase relationship. Reset is not required if the phase relationships are not important to your application.
- Resetting the I/O PLL does not modify the counter or loop filter settings. However, resetting the I/O PLL undoes any dynamic phase shift operations that were performed. After the I/O PLL is reset, the phase shift on the C counters is restored to the originally programmed settings.