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1. Intel® Agilex™ Clocking and PLL Overview
2. Intel® Agilex™ Clocking and PLL Architecture and Features
3. Intel® Agilex™ Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Intel® Agilex™ Clocking and PLL User Guide Archives
8. Document Revision History for the Intel® Agilex™ Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Guidelines: I/O PLL Reconfiguration
3.6. Clocking Constraints
3.7. IP Core Constraints
3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core
6.3. IOPLL Reconfig IP Core Reconfiguration Modes
6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
6.5. Address Bus and Data Bus Settings
6.6. Design Example
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6.5.1.1. Data Bus Setting for Bandwidth Control and Charge Pump
Multiply Factor 15 | Low Bandwidth | ||
---|---|---|---|
Bandwidth Control Setting Data [6:3] |
Charge Pump Setting [2:0] Address = 00000001 Data [6:4] |
Charge Pump Setting [5:3] Address = 00001101 Data [7:5] |
|
4–5 | 4'b0011 | 3'b011 | 3'b000 |
6–7 | 4'b0011 | 3'b011 | 3'b000 |
8–10 | 4'b0011 | 3'b100 | 3'b000 |
11–15 | 4'b0100 | 3'b100 | 3'b000 |
16–20 | 4'b0101 | 3'b100 | 3'b000 |
21–23 | 4'b0101 | 3'b101 | 3'b000 |
24–43 | 4'b0110 | 3'b100 | 3'b000 |
44–64 | 4'b0111 | 3'b100 | 3'b000 |
65–85 | 4'b1000 | 3'b100 | 3'b000 |
86–124 | 4'b1010 | 3'b011 | 3'b000 |
125–160 | 4'b1010 | 3'b011 | 3'b000 |
Multiply Factor 15 | Medium Bandwidth | ||
---|---|---|---|
Bandwidth Control Setting Data [6:3] |
Charge Pump Setting [2:0] Address = 00000001 Data [6:4] |
Charge Pump Setting [5:3] Address = 00001101 Data [7:5] |
|
4–5 | 4'b0010 | 3'b110 | 3'b000 |
6–7 | 4'b0011 | 3'b101 | 3'b000 |
8–10 | 4'b0011 | 3'b101 | 3'b000 |
11–15 | 4'b0011 | 3'b110 | 3'b000 |
16–20 | 4'b0100 | 3'b110 | 3'b000 |
21–23 | 4'b0100 | 3'b111 | 3'b000 |
24–43 | 4'b0101 | 3'b110 | 3'b000 |
44–64 | 4'b0110 | 3'b110 | 3'b000 |
65–85 | 4'b0111 | 3'b110 | 3'b000 |
86–124 | 4'b1000 | 3'b110 | 3'b000 |
125–160 | 4'b1010 | 3'b100 | 3'b000 |
Multiply Factor 15 | High Bandwidth | ||
---|---|---|---|
Bandwidth Control Setting Data [6:3] |
Charge Pump Setting [2:0] Address = 00000001 Data [6:4] |
Charge Pump Setting [5:3] Address = 00001101 Data [7:5] |
|
4–5 | 4'b0010 | 3'b001 | 3'b001 |
6–7 | 4'b0010 | 3'b010 | 3'b001 |
8–10 | 4'b0010 | 3'b011 | 3'b001 |
11–15 | 4'b0011 | 3'b001 | 3'b001 |
16–20 | 4'b0011 | 3'b010 | 3'b001 |
21–23 | 4'b0100 | 3'b010 | 3'b001 |
24–43 | 4'b0100 | 3'b011 | 3'b001 |
44–64 | 4'b0101 | 3'b011 | 3'b001 |
65–85 | 4'b0101 | 3'b011 | 3'b001 |
86–124 | 4'b1001 | 3'b110 | 3'b000 |
125–160 | 4'b1001 | 3'b110 | 3'b000 |
Multiply Factor 15 | Medium Bandwidth | ||
---|---|---|---|
Bandwidth Control Setting Data [6:3] |
Charge Pump Setting [2:0] Address = 00000001 Data [6:4] |
Charge Pump Setting [5:3] Address = 00001101 Data [7:5] |
|
4–5 | 4'b0011 | 3'b100 | 3'b000 |
6–7 | 4'b0100 | 3'b100 | 3'b000 |
8–10 | 4'b0101 | 3'b100 | 3'b000 |
11–15 | 4'b0110 | 3'b100 | 3'b000 |
16–20 | 4'b0111 | 3'b100 | 3'b000 |
21–23 | 4'b0111 | 3'b100 | 3'b000 |
24–43 | 4'b1001 | 3'b011 | 3'b000 |
44–64 | 4'b1010 | 3'b011 | 3'b000 |
65–85 | 4'b1010 | 3'b100 | 3'b000 |
86–104 | 4'b1010 | 3'b101 | 3'b000 |
105–140 | 4'b1011 | 3'b100 | 3'b000 |
141–160 | 4'b1011 | 3'b100 | 3'b000 |
Multiply Factor 15 | High Bandwidth | ||
---|---|---|---|
Bandwidth Control Setting Data [6:3] |
Charge Pump Setting [2:0] Address = 00000001 Data [6:4] |
Charge Pump Setting [5:3] Address = 00001101 Data [7:5] |
|
4–5 | 4'b0010 | 3'b001 | 3'b001 |
6–7 | 4'b0011 | 3'b000 | 3'b001 |
8–10 | 4'b0011 | 3'b000 | 3'b001 |
11–15 | 4'b0100 | 3'b000 | 3'b001 |
16–20 | 4'b0110 | 3'b110 | 3'b000 |
21–23 | 4'b0111 | 3'b101 | 3'b000 |
24–43 | 4'b1000 | 3'b101 | 3'b000 |
44–64 | 4'b1001 | 3'b101 | 3'b000 |
65–85 | 4'b1001 | 3'b110 | 3'b000 |
86–104 | 4'b1001 | 3'b110 | 3'b000 |
105–140 | 4'b1010 | 3'b101 | 3'b000 |
141–160 | 4'b1010 | 3'b101 | 3'b000 |
15 If you select the Use Nondedicated Feedback Path option under the Normal or Source Synchronous compensation mode, the Multiply Factor is M x C i , where M is M counter value while C i is the Compensated Outclk C counter value. Else, the Multiply Factor is only the M counter value.
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