Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
Document Table of Contents

6.6.1. Reconfiguration Option: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core

After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration at medium bandwidth:

  • 400 MHz with 0 ps phase shift on counter C1 output
  • 200 MHz with 0 ps phase shift on counter C2 output

To run the design example using .mif streaming reconfiguration, perform these steps:

  1. Open AN.stp file and program the device top.sof.
  2. In the In-System Sources & Probes IP core parameter editor, ensure the mode_0 and mode_1 inputs remain in low pulse.
  3. Assert a high pulse on the reset_SM signal to start the I/O PLL reconfiguration operation.
Figure 26. Waveform Example for .mif Streaming Reconfiguration Design Example

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