The locked signal port of the IP core for the I/O PLL is locked.
The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock locks onto the reference clock both in phase and frequency.
PLL loses lock if the input reference clock stops toggling. When PLL loses lock, the output of the PLL starts drifting out of the desired frequency. The downstream logic must be held inactive when PLL has lost lock.
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