Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 11/09/2022

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3.5. Guidelines: I/O PLL Reconfiguration

To reconfigure the I/O PLL, refer to the following guidelines:

  • If the reference clock frequency changes, you must recalibrate the I/O PLL using the IP core.
  • The I/O PLL reconfiguration interface must have a free running mgmt_clk signal. The mgmt_clk signal must be less than 100 MHz. This interface eliminates the need to precisely control the start and stop of mgmt_clk signal.
  • The I/O PLL can be reconfigured with .mif streaming mode and advanced mode using the IP core. Intel recommends using the .mif streaming mode.
  • Use caution when reconfiguring an I/O PLL with a non-zero phase shift setting. Modifying the M counter or N counter settings does not change the relative phase shift (in percent), but alters the absolute phase shift (in picoseconds). Modifying the C counter settings does not change the absolute phase shift, but modifies the relative phase shift.