5. IOPLL Intel® FPGA IP Core
The IOPLL IP core allows you to configure the settings of the Intel® Agilex™ I/O PLL.
The IOPLL IP core supports the following features:
- Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
- Generates up to seven output clocks for I/O bank I/O PLL and three output clocks for fabric-feeding I/O PLL for the Intel® Agilex™ device.
- Switches between two reference input clocks.
- Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL dedicated cascading mode.
- Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
- Supports PLL dynamic phase shift.
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