6.6.3. Reconfiguration Option: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration at medium bandwidth:
- Counter C1 output is ungated
- Counter C2 output is gated
To run the design example using clock gating reconfiguration, perform these steps:
- Open AN.stp file and program the device top.sof.
- In the In-System Sources & Probes IP core, keep mode_0 in low pulse and assert mode_1 to high pulse.
- Assert a high pulse on the reset_SM signal to start the I/O PLL reconfiguration operation.
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