Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
Document Table of Contents

6.6. Design Example

This design example uses a AGFB014R24A2E3VR0 device to demonstrate the implementation of the following three different I/O PLL reconfiguration options using the IOPLL Reconfig IP core:

  • .mif streaming reconfiguration
  • Advanced mode reconfiguration
  • Clock gating reconfiguration

You must install the Intel® Quartus® Prime software version 20.1 or later. The software must be installed on a Windows* or Linux* computer that meets the Intel® Quartus® Prime software minimum requirements.

This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, In-System Sources & Probes Intel® FPGA IP core, and Reset Release Intel FPGA IP core.

Before reconfiguration, the I/O PLL synthesizes two output clocks of 150 MHz and 300 MHz on counter C1 and counter C2 output, respectively, at medium bandwidth. The input reference clock is 100 MHz.

The IOPLL Reconfig IP core connects to a state machine to perform I/O PLL reconfiguration operation. A high pulse on the reset_SM signal triggers the I/O PLL reconfiguration operation. The desired reconfiguration mode can be selected through mode_0 and mode_1 inputs. These inputs are controlled through the In-System Sources & Probes IP core.

Table 28.  Reconfiguration Mode Selection for the Design Example
Reconfiguration Mode mode_1 mode_0
.mif streaming reconfiguration 0 0
Advanced mode reconfiguration 0 1
Clock gating reconfiguration 1 0

Download and restore the Design Example (iopll-reconfig.qar) file. Change the device and pin assignments of the design example to match your hardware. Ensure MIF file path in the IOPLL Reconfig IP core is set to the .mif file path in the project of the design example. Recompile the design example and ensure that the design example does not contain any timing violation after reconfiguration

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