Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 3/26/2022
Public
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3.2. Guidelines: Timing Closure

For timing closure, refer to the following guidelines:

  • Reconfiguring a PLL's counter and loop filter settings changes both the output frequency and the clock uncertainty of that I/O PLL. Dynamic phase shift only affects the output clock phase.
  • The Intel® Quartus® Prime Timing Analyzer performs timing analysis for the initial PLL settings only. You must verify that your design closes timing after dynamic reconfiguration or dynamic phase shift.
  • Intel recommends compiling the I/O PLL designs with each intended configuration setting to determine the variation in the clock with the I/O PLL settings.

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