2.5. Technology Map Viewer Overview
The Technology Map Viewer shows the hierarchy of atom primitives (such as device logic cells and I/O ports) in the design. For supported device families, you can also view internal registers and look-up tables (LUTs) inside logic cells (LCELLs), and registers in I/O atom primitives.
Where possible, the Intel® Quartus® Prime software maintains the port names of each hierarchy throughout synthesis. However, the software may change or remove port names from the design. For example, the software removes ports that are unconnected or driven by GND or VCC during synthesis. If a port name changes, the software assigns a related user logic name in the design or a generic port name such as IN1 or OUT1.
You can view Intel® Quartus® Prime technology-mapped results after synthesis, fitting, or timing analysis. To run the Technology Map Viewer for a Intel® Quartus® Prime project, on the Processing menu, point to Start and click Start Analysis & Synthesis to synthesize and map the design to the target technology. At this stage, the Technology Map Viewer shows the same post-mapping netlist as the Technology Map Viewer (Post‑Mapping). You can also perform a full compilation, or any process that includes the synthesis stage in the compilation flow.
For designs that completed the Fitter stage, the Technology Map Viewer shows how the Fitter changed the netlist through physical synthesis optimizations, while the Technology Map Viewer (Post‑Mapping) shows the post-mapping netlist. If you have completed the Timing Analysis stage, you can locate timing paths from the Timing Analyzer report in the Technology Map Viewer.
To open the Technology Map Viewer, click Tools > Netlist Viewers > Technology Map Viewer (Post-Fitting) or Technology Map Viewer (Post Mapping).
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