5.1.3. Viewing Architecture-Specific Design Information
- Device routing resources used by your design—View how blocks are connected, as well as the signal routing that connects the blocks.
- LE configuration—View logic element (LE) configuration in your design. For example, you can view which LE inputs are used; whether the LE utilizes the register, the look-up table (LUT), or both; as well as the signal flow through the LE.
- ALM configuration—View ALM configuration in your design. For example, you can view which ALM inputs are used; whether the ALM utilizes the registers, the upper LUT, the lower LUT, or all of them. You can also view the signal flow through the ALM.
- I/O configuration—View device I/O resource usage. For example, you can view which components of the I/O resources are used, whether the delay chain settings are enabled, which I/O standards are set, and the signal flow through the I/O.
- PLL configuration—View phase-locked loop (PLL) configuration in your design. For example, you can view which control signals of the PLL are used with the settings for your PLL.
- Timing—View the delay between the inputs and outputs of FPGA elements. For example, you can analyze the timing of the DATAB input to the COMBOUT output.
In addition, you can modify the following device properties with the Chip Planner:
- LEs and ALMs
- I/O cells
- Registers in RAM and DSP blocks
- Connections between elements
- Placement of elements
For more information about LEs, ALMs, and other resources of an FPGA device, refer to the relevant device handbook.
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