Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

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ID 683230
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
1. Design Optimization Overview 2. Optimizing the Design Netlist 3. Timing Closure and Optimization 4. Area Optimization 5. Analyzing and Optimizing the Design Floorplan 6. Netlist Optimizations and Physical Synthesis 7. Engineering Change Orders with the Chip Planner A. Intel® Quartus® Prime Standard Edition User Guides
1. Design Optimization Overview x
1.1. Device Considerations 1.2. Required Settings for Initial Compilation 1.3. Trade-Offs and Limitations 1.4. Intel® Quartus® Prime Software Tools for Design Optimization 1.5. Design Space Explorer II 1.6. Design Optimization Overview Revision History
1.1. Device Considerations x
1.1.1. Device Migration Considerations
1.2. Required Settings for Initial Compilation x
1.2.1. Guidelines for I/O Assignments 1.2.2. Guidelines for Time Constraints 1.2.3. Partitions and Floorplan Assignments for Incremental Compilation
1.3. Trade-Offs and Limitations x
1.3.1. Preserving Results and Enabling Teamwork 1.3.2. Reducing Area 1.3.3. Reducing Critical Path Delay 1.3.4. Reducing Power Consumption 1.3.5. Reducing Runtime
1.4. Intel® Quartus® Prime Software Tools for Design Optimization x
1.4.1. Design Visualization Tools 1.4.2. Advisors 1.4.3. Design Exploration
1.5. Design Space Explorer II x
1.5.1. How DSE II Works 1.5.2. Performing a Design Exploration with the DSE II Utility
1.5.1. How DSE II Works x
1.5.1.1. Use of Computing Resources 1.5.1.2. Optimization Parameters 1.5.1.3. Result Management
2. Optimizing the Design Netlist x
2.1. When to Use the Netlist Viewers: Analyzing Design Problems 2.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers 2.3. RTL Viewer Overview 2.4. State Machine Viewer Overview 2.5. Technology Map Viewer Overview 2.6. Netlist Viewer User Interface 2.7. Schematic View 2.8. State Machine Viewer 2.9. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows 2.10. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows 2.11. Viewing a Timing Path 2.12. Optimizing the Design Netlist Revision History
2.3. RTL Viewer Overview x
2.3.1. Maximizing Readability in RTL Viewer 2.3.2. Running the RTL Viewer
2.6. Netlist Viewer User Interface x
2.6.1. Netlist Navigator Pane 2.6.2. Properties Pane 2.6.3. Netlist Viewers Find Pane
2.7. Schematic View x
2.7.1. Display Schematics in Multiple Tabbed View 2.7.2. Schematic Symbols 2.7.3. Select Items in the Schematic View 2.7.4. Shortcut Menu Commands in the Schematic View 2.7.5. Filtering in the Schematic View 2.7.6. View Contents of Nodes in the Schematic View 2.7.7. Moving Nodes in the Schematic View 2.7.8. View LUT Representations in the Technology Map Viewer 2.7.9. Zoom Controls 2.7.10. Navigating with the Bird's Eye View 2.7.11. Partition the Schematic into Pages 2.7.12. Follow Nets Across Schematic Pages
2.8. State Machine Viewer x
2.8.1. State Diagram View 2.8.2. State Transition Table 2.8.3. State Encoding Table 2.8.4. Switch Between State Machines
2.8.3. State Encoding Table x
2.8.3.1. Select Items in the State Machine Viewer
3. Timing Closure and Optimization x
3.1. Optimize Multi Corner Timing 3.2. Critical Paths 3.3. Design Evaluation for Timing Closure 3.4. Design Analysis 3.5. Timing Optimization 3.6. Periphery to Core Register Placement and Routing Optimization 3.77.7. Scripting Support3.77.7. Scripting Support 3.8. Timing Closure and Optimization Revision History
3.2. Critical Paths x
3.2.1. Viewing Critical Paths
3.3. Design Evaluation for Timing Closure x
3.3.1. Review Compilation Results 3.3.2. Review Details of Timing Paths 3.3.3. Adjusting and Recompiling
3.3.1. Review Compilation Results x
3.3.1.1. Review Messages 3.3.1.2. Evaluate Physical Synthesis Results 3.3.1.3. Evaluate Fitter Netlist Optimizations 3.3.1.4. Evaluate Optimization Results 3.3.1.5. Evaluate Resource Usage 3.3.1.6. Evaluate Other Reports and Adjust Settings Accordingly 3.3.1.7. Evaluate Clustering Difficulty
3.3.1.5. Evaluate Resource Usage x
3.3.1.5.1. Global and Non-Global Usage 3.3.1.5.2. Routing Usage 3.3.1.5.3. Wires Added for Hold
3.3.2. Review Details of Timing Paths x
3.3.2.1. Show Timing Path Routing 3.3.2.2. Global Network Buffers 3.3.2.3. Resets and Global Networks 3.3.2.4. Suspicious Setup 3.3.2.5. Logic Depth 3.3.2.6. Auto Shift Register Replacement 3.3.2.7. Clocking Architecture 3.3.2.8. Timing Closure Recommendations
3.3.2.2. Global Network Buffers x
3.3.2.2.1. Source Location 3.3.2.2.2. Insertion Delay 3.3.2.2.3. Fan-Out 3.3.2.2.4. Global Networks
3.3.3. Adjusting and Recompiling x
3.3.3.1. Using Partitions to Achieve Timing Closure
3.4. Design Analysis x
3.4.1. Ignored Timing Constraints 3.4.2. I/O Timing 3.4.3. Register-to-Register Timing Analysis
3.4.3. Register-to-Register Timing Analysis x
3.4.3.1. Displaying Path Reports with the Timing Analyzer 3.4.3.2. Tips for Analyzing Failing Paths 3.4.3.3. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 3.4.3.4. Tips for Analyzing Paths from/to the Source and Destination of Critical Path 3.4.3.5. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 3.4.3.6. Global Routing Resources
3.5. Timing Optimization x
3.5.1. Displaying Timing Closure Recommendations for Failing Paths 3.5.2. Timing Optimization Advisor 3.5.3. Optional Fitter Settings 3.5.4. I/O Timing Optimization Techniques 3.5.5. Register-to-Register Timing Optimization Techniques 3.5.6. Logic Lock (Standard) Assignments 3.5.7. Location Assignments 3.5.8. Metastability Analysis and Optimization Techniques
3.5.3. Optional Fitter Settings x
3.5.3.1. Optimize Hold Timing 3.5.3.2. Fitter Aggressive Routability Optimization
3.5.4. I/O Timing Optimization Techniques x
3.5.4.1. Optimize IOC Register Placement for Timing Logic Option 3.5.4.2. Fast Input, Output, and Output Enable Registers 3.5.4.3. Programmable Delays 3.5.4.4. Use PLLs to Shift Clock Edges 3.5.4.5. Use Fast Regional Clock Networks and Regional Clocks Networks 3.5.4.6. Spine Clock Limitations 3.5.4.7. Change How Hold Times are Optimized for Devices
3.5.5. Register-to-Register Timing Optimization Techniques x
3.5.5.1. Optimize Source Code 3.5.5.2. Improving Register-to-Register Timing 3.5.5.3. Physical Synthesis Optimizations 3.5.5.4. Turn Off Extra-Effort Power Optimization Settings 3.5.5.5. Optimize Synthesis for Speed, Not Area 3.5.5.6. Flatten the Hierarchy During Synthesis 3.5.5.7. Set the Synthesis Effort to High 3.5.5.8. Change State Machine Encoding 3.5.5.9. Duplicate Logic for Fan-Out Control 3.5.5.10. Prevent Shift Register Inference 3.5.5.11. Use Other Synthesis Options Available in Your Synthesis Tool 3.5.5.12. Fitter Seed 3.5.5.13. Set Maximum Router Timing Optimization Level
3.5.6. Logic Lock (Standard) Assignments x
3.5.6.1. Hierarchy Assignments
3.6. Periphery to Core Register Placement and Routing Optimization x
3.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box 3.6.2. Setting Periphery to Core Optimizations in the Assignment Editor 3.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
3.77.7. Scripting Support3.77.7. Scripting Support x
3.7.1. Initial Compilation Settings 3.7.2. I/O Timing Optimization Techniques 3.7.3. Register-to-Register Timing Optimization Techniques
4. Area Optimization x
4.1. Resource Utilization Information 4.2. Optimizing Resource Utilization 4.3. Scripting Support 4.4. Area Optimization Revision History
4.1. Resource Utilization Information x
4.1.1. Flow Summary Report 4.1.2. Fitter Reports 4.1.3. Analysis and Synthesis Reports 4.1.4. Compilation Messages
4.2. Optimizing Resource Utilization x
4.2.1. Using the Resource Optimization Advisor 4.2.2. Resource Utilization Issues Overview 4.2.3. I/O Pin Utilization or Placement 4.2.4. Logic Utilization or Placement 4.2.5. Routing
4.2.3. I/O Pin Utilization or Placement x
4.2.3.1. Guideline: Use I/O Assignment Analysis 4.2.3.2. Guideline: Modify Pin Assignments or Choose a Larger Package
4.2.4. Logic Utilization or Placement x
4.2.4.1. Guideline: Optimize Source Code 4.2.4.2. Guideline: Optimize Synthesis for Area, Not Speed 4.2.4.3. Guideline: Restructure Multiplexers 4.2.4.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 4.2.4.5. Guideline: Use Register Packing 4.2.4.6. Guideline: Remove Fitter Constraints 4.2.4.7. Guideline: Flatten the Hierarchy During Synthesis 4.2.4.8. Guideline: Re-target Memory Blocks 4.2.4.9. Guideline: Use Physical Synthesis Options to Reduce Area 4.2.4.10. Guideline: Retarget or Balance DSP Blocks 4.2.4.11. Guideline: Use a Larger Device
4.2.5. Routing x
4.2.5.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 4.2.5.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always 4.2.5.3. Guideline: Increase Router Effort Multiplier 4.2.5.4. Guideline: Remove Fitter Constraints 4.2.5.5. Guideline: Optimize Synthesis for Area, Not Speed 4.2.5.6. Guideline: Optimize Source Code 4.2.5.7. Guideline: Use a Larger Device
4.3. Scripting Support x
4.3.1. Initial Compilation Settings 4.3.2. Resource Utilization Optimization Techniques
5. Analyzing and Optimizing the Design Floorplan x
5.1. Design Floorplan Analysis in the Chip Planner 5.2. Logic Lock (Standard) Regions 5.3. Using Logic Lock (Standard) Regions in the Chip Planner 5.4. Scripting Support 5.5. Analyzing and Optimizing the Design Floorplan Revision History
5.1. Design Floorplan Analysis in the Chip Planner x
5.1.1. Starting the Chip Planner 5.1.2. Chip Planner GUI Components 5.1.3. Viewing Architecture-Specific Design Information 5.1.4. Viewing Available Clock Networks in the Device 5.1.5. Viewing Routing Congestion 5.1.6. Viewing I/O Banks 5.1.7. Viewing High-Speed Serial Interfaces (HSSI) 5.1.8. Viewing the Source and Destination of Placed Nodes 5.1.9. Viewing Fan-In and Fan-Out Connections of Placed Resources 5.1.10. Generating Immediate Fan-In and Fan-Out Connections 5.1.11. Exploring Paths in the Chip Planner 5.1.12. Viewing Assignments in the Chip Planner 5.1.13. Viewing High-Speed and Low-Power Tiles in the Chip Planner 5.1.14. Viewing Design Partition Placement
5.1.2. Chip Planner GUI Components x
5.1.2.1. Chip Planner Toolbar 5.1.2.2. Layers Settings and Editing Modes 5.1.2.3. Locate History Window 5.1.2.4. Chip Planner Floorplan Views
5.1.11. Exploring Paths in the Chip Planner x
5.1.11.1. Analyzing Connections for a Path 5.1.11.2. Locate Path from the Timing Analysis Report to the Chip Planner 5.1.11.3. Show Delays 5.1.11.4. Viewing Routing Resources
5.2. Logic Lock (Standard) Regions x
5.2.1. Attributes of a Logic Lock (Standard) Region 5.2.2. Creating Logic Lock (Standard) Regions 5.2.3. Customizing the Shape of Logic Lock Regions 5.2.4. Placing Logic Lock (Standard) Regions 5.2.5. Placing Device Resources into Logic Lock (Standard) Regions 5.2.6. Hierarchical (Parent and Child) Logic Lock (Standard) Regions 5.2.7. Additional Intel® Quartus® Prime Logic Lock (Standard) Design Features 5.2.8. Logic Lock (Standard) Regions Window
5.2.2. Creating Logic Lock (Standard) Regions x
5.2.2.1. Creating Logic Lock (Standard) Regions with the Chip Planner 5.2.2.2. Creating Logic Lock (Standard) Regions with the Project Navigator 5.2.2.3. Creating Logic Lock (Standard) Regions with the Logic Lock (Standard) Regions Window 5.2.2.4. Defining Routing Regions 5.2.2.5. Noncontiguous Logic Lock (Standard) Regions 5.2.2.6. Considerations on Using Auto Sized Regions
5.2.3. Customizing the Shape of Logic Lock Regions x
5.2.3.1. Merging Logic Lock (Standard) Regions 5.2.3.2. Noncontiguous Logic Lock (Standard) Regions
5.2.5. Placing Device Resources into Logic Lock (Standard) Regions x
5.2.5.1. Empty Logic Lock Regions 5.2.5.2. Pin Assignment 5.2.5.3. Reserved Logic Lock (Standard) Regions 5.2.5.4. Excluded Resources 5.2.5.5. Logic Lock (Standard) Assignment Precedence 5.2.5.6. Virtual Pins
5.2.7. Additional Intel® Quartus® Prime Logic Lock (Standard) Design Features x
5.2.7.1. Analysis and Synthesis Resource Utilization by Entity 5.2.7.2. Intel® Quartus® Prime Revisions Feature
5.3. Using Logic Lock (Standard) Regions in the Chip Planner x
5.3.1. Viewing Connections Between Logic Lock (Standard) Regions in the Chip Planner 5.3.2. Using Logic Lock (Standard) Regions with the Design Partition Planner
5.4. Scripting Support x
5.4.1. Initializing and Uninitializing a Logic Lock (Standard) Region 5.4.2. Creating or Modifying Logic Lock (Standard) Regions 5.4.3. Obtaining Logic Lock (Standard) Region Properties 5.4.4. Assigning Logic Lock (Standard) Region Content 5.4.5. Save a Node-Level Netlist for the Entire Design into a Persistent Source File 5.4.6. Setting Logic Lock (Standard) Assignment Priority 5.4.7. Assigning Virtual Pins with a Tcl command
6. Netlist Optimizations and Physical Synthesis x
6.1. Physical Synthesis Optimizations 6.2. Applying Netlist Optimizations 6.3. Viewing Synthesis and Netlist Optimization Reports 6.4. Scripting Support 6.5. Netlist Optimizations and Physical Synthesis Revision History
6.1. Physical Synthesis Optimizations x
6.1.1. Enabling Physical Synthesis Optimization 6.1.2. Physical Synthesis Options 6.1.3. Perform Register Retiming for Performance 6.1.4. Preventing Register Movement During Retiming
6.2. Applying Netlist Optimizations x
6.2.1. WYSIWYG Primitive Resynthesis 6.2.2. Saving a Node-Level Netlist
6.4. Scripting Support x
6.4.1. Synthesis Netlist Optimizations 6.4.2. Physical Synthesis Optimizations 6.4.3. Back-Annotating Assignments
7. Engineering Change Orders with the Chip Planner x
7.1. Engineering Change Orders 7.2. ECO Design Flow 7.3. The Chip Planner Overview 7.4. Performing ECOs with the Chip Planner (Floorplan View) 7.5. Performing ECOs in the Resource Property Editor 7.6. Change Manager 3.77.7. Scripting Support3.77.7. Scripting Support 7.8. Common ECO Applications 7.9. Post ECO Steps 7.10. Engineering Change Orders with the Chip Planner Revision History
7.1. Engineering Change Orders x
7.1.1. Performance Preservation 7.1.2. Compilation Time 7.1.3. Verification 7.1.4. Change Modification Record
7.3. The Chip Planner Overview x
7.3.1. Opening the Chip Planner 7.3.2. The Chip Planner Tasks and Layers
7.4. Performing ECOs with the Chip Planner (Floorplan View) x
7.4.1. Creating, Deleting, and Moving Atoms 7.4.2. Check and Save Netlist Changes
7.5. Performing ECOs in the Resource Property Editor x
7.5.1. Logic Elements 7.5.2. Adaptive Logic Modules 7.5.3. FPGA I/O Elements 7.5.4. FPGA RAM Blocks 7.5.5. FPGA DSP Blocks
7.5.1. Logic Elements x
7.5.1.1. Logic Element Properties 7.5.1.2. Modes of Operation 7.5.1.3. Sum and Carry Equations 7.5.1.4. sload and sclr Signals 7.5.1.5. Register Cascade Mode 7.5.1.6. Cell Delay Table 7.5.1.7. Logic Element Connections 7.5.1.8. Deleting a Logic Element
7.5.2. Adaptive Logic Modules x
7.5.2.1. Adaptive Logic Module Schematic 7.5.2.2. Adaptive Logic Module Properties 7.5.2.3. Adaptive Logic Module Connections
7.5.3. FPGA I/O Elements x
7.5.3.1. Stratix V I/O Elements 7.5.3.2. Stratix IV I/O Elements 7.5.3.3. Arria V I/O Elements 7.5.3.4. Cyclone V I/O Elements 7.5.3.5. MAX V I/O Elements
7.6. Change Manager x
7.6.1. Complex Changes in the Change Manager 7.6.2. Managing Signal Probe Signals 7.6.3. Exporting Changes
7.8. Common ECO Applications x
7.8.1. Adjust the Drive Strength of an I/O with the Chip Planner 7.8.2. Modify the PLL Properties With the Chip Planner 7.8.3. PLL Properties 7.8.4. Modify the Connectivity between Resource Atoms
7.8.3. PLL Properties x
7.8.3.1. Adjusting the Duty Cycle 7.8.3.2. Adjusting the Phase Shift 7.8.3.3. Adjusting the Output Clock Frequency 7.8.3.4. Adjusting the Spread Spectrum
1. Design Optimization Overview
2. Optimizing the Design Netlist
3. Timing Closure and Optimization
4. Area Optimization
5. Analyzing and Optimizing the Design Floorplan
6. Netlist Optimizations and Physical Synthesis
7. Engineering Change Orders with the Chip Planner
A. Intel® Quartus® Prime Standard Edition User Guides

6.1.4. Preventing Register Movement During Retiming

If you want to prevent register movement during register retiming, you can set the Netlist Optimizations logic option to Never Allow. You can apply this option to either individual registers or entities in the design using the Assignment Editor.

In digital circuits, synchronization registers are instantiated on cross clock domain paths to reduce the possibility of metastability. The Intel® Quartus® Prime software detects such synchronization registers and does not move them, even if register retiming is turned on.

The following sets of registers are not moved during register retiming:

  • Both registers in a direct connection from input pin-to-register-to-register if both registers have the same clock and the first register does not fan-out to anywhere else. These registers are considered synchronization registers.
  • Both registers in a direct connection from register-to-register if both registers have the same clock, the first register does not fan out to anywhere else, and the first register is fed by another register in a different clock domain (directly or through combinational logic). These registers are considered synchronization registers.

The Intel® Quartus® Prime software does not perform register retiming on logic cells that have the following properties:

  • Are part of a cascade chain
  • Contain registers that drive asynchronous control signals on another register
  • Contain registers that drive the clock of another register
  • Contain registers that drive a register in another clock domain
  • Contain registers that are driven by a register in another clock domain
Note: The Intel® Quartus® Prime software does not usually retime registers across different clock domains; however, if you use the Classic Timing Analyzer and specify a global fMAX requirement, the Intel® Quartus® Prime software interprets all clocks as related. Consequently, the Intel® Quartus® Prime software might try to retime register-to-register paths associated with different clocks.

To avoid this circumstance, provide individual fMAX requirements to each clock when using Classic Timing Analysis. When you constrain each clock individually, the Intel® Quartus® Prime software assumes no relationship between different clock domains and considers each clock domain to be asynchronous to other clock domains; hence no register-to-register paths crossing clock domains are retimed.

When you use the Timing Analyzer, register-to-register paths across clock domains are never retimed, because the Timing Analyzer treats all clock domains as asynchronous to each other unless they are intentionally grouped.
  • Contain registers that are constrained to a single LAB location
  • Contain registers that are connected to SERDES
  • Are considered virtual I/O pins
  • Registers that have the Netlist Optimizations logic option set to Never Allow

The Intel® Quartus® Prime software assumes that a synchronization register chain consists of two registers. If your design has synchronization register chains with more than two registers, you must indicate the number of registers in your synchronization chains so that they are not affected by register retiming. To do this, perform the following steps:

  1. Click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).
  2. Modify the Synchronization Register Chain Length setting to match the synchronization register length used in your design. If you set a value of 1 for the Synchronization Register Chain Length, it means that any registers connected to the first register in a register-to-register connection can be moved during retiming. A value of n > 1 means that any registers in a sequence of length 1, 2,… n are not moved during register retiming.

    If you want to consider logic cells that meet any of these conditions for physical synthesis, you can override these rules by setting the Netlist Optimizations logic option to Always Allow on a given set of registers.

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