6.1.4. Preventing Register Movement During Retiming
In digital circuits, synchronization registers are instantiated on cross clock domain paths to reduce the possibility of metastability. The Intel® Quartus® Prime software detects such synchronization registers and does not move them, even if register retiming is turned on.
The following sets of registers are not moved during register retiming:
- Both registers in a direct connection from input pin-to-register-to-register if both registers have the same clock and the first register does not fan-out to anywhere else. These registers are considered synchronization registers.
- Both registers in a direct connection from register-to-register if both registers have the same clock, the first register does not fan out to anywhere else, and the first register is fed by another register in a different clock domain (directly or through combinational logic). These registers are considered synchronization registers.
The Intel® Quartus® Prime software does not perform register retiming on logic cells that have the following properties:
- Are part of a cascade chain
- Contain registers that drive asynchronous control signals on another register
- Contain registers that drive the clock of another register
- Contain registers that drive a register in another clock domain
- Contain registers that are driven by a register in another clock domain
- Contain registers that are constrained to a single LAB location
- Contain registers that are connected to SERDES
- Are considered virtual I/O pins
- Registers that have the Netlist Optimizations logic option set to Never Allow
The Intel® Quartus® Prime software assumes that a synchronization register chain consists of two registers. If your design has synchronization register chains with more than two registers, you must indicate the number of registers in your synchronization chains so that they are not affected by register retiming. To do this, perform the following steps:
- Click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).
- Modify the Synchronization Register Chain Length setting to match the synchronization register length used in your design. If you set a value of 1 for the Synchronization Register Chain Length, it means that any registers connected to the first register in a register-to-register connection can be moved during retiming. A value of n > 1 means that any registers in a sequence of length 1, 2,… n are not moved during register retiming.
If you want to consider logic cells that meet any of these conditions for physical synthesis, you can override these rules by setting the Netlist Optimizations logic option to Always Allow on a given set of registers.
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