184.108.40.206. Virtual Pins
When you apply the Virtual Pin assignment to an input pin, the pin no longer appears as an FPGA pin; the Compiler fixes the virtual pin to GND in the design. The virtual pin is not a floating node.
Use virtual pins only for I/O elements in lower-level design entities that become nodes after you import the entity to the top-level design; for example, when compiling a partial design.
In the top-level design, you connect these virtual pins to an internal node of another module. By making assignments to virtual pins, you can place those pins in the same location or region on the device as that of the corresponding internal nodes in the top-level module. You can use the Virtual Pin option when compiling a Logic Lock (Standard) module with more pins than the target device allows. The Virtual Pin option can enable timing analysis of a design module that more closely matches the performance of the module after you integrate it into the top-level design.
To display all assigned virtual pins in the design with the Node Finder, you can set Filter Type to Pins: Virtual. To access the Node Finder from the Assignment Editor, double-click the To field; when the arrow appears on the right side of the field, click and select Node Finder.
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