Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

6.2.1. WYSIWYG Primitive Resynthesis

For designs synthesized with a third-party tool, the Perform WYSIWYG primitive resynthesis option allows you to apply optimizations to the synthesized netlist.

The Perform WYSIWYG primitive resynthesis option directs the Intel® Quartus® Prime software to un-map the logic elements (LEs) in an atom netlist to logic gates, and then re-map the gates back to Intel-specific primitives. Third-party synthesis tools generate either an .edf or .vqm atom netlist file using Intel-specific primitives. When you turn on the Perform WYSIWYG primitive resynthesis option, the Intel® Quartus® Prime software uses device-specific techniques during the re-mapping process. This feature re-maps the design using the Optimization Technique specified for your project (Speed, Area, or Balanced).

The Perform WYSIWYG primitive resynthesis option unmaps and remaps only logic cells, also referred to as LCELL or LE primitives, and regular I/O primitives (which may contain registers). Double data rate (DDR) I/O primitives, memory primitives, digital signal processing (DSP) primitives, and logic cells in carry/cascade chains are not remapped. This process does not process logic specified in an encrypted .vqm file or an .edf file, such as third-party intellectual property (IP).

The Perform WYSIWYG primitive resynthesisoption can change node names in the .vqm file or .edf file from your third-party synthesis tool, because the primitives in the atom netlist are broken apart and then re-mapped by the Intel® Quartus® Prime software. The re-mapping process removes duplicate registers. Registers that are not removed retain the same name after re-mapping.

Any nodes or entities that have the Netlist Optimizations logic option set to Never Allow are not affected during WYSIWYG primitive resynthesis. You can use the Assignment Editor to apply the Netlist Optimizations logic option. This option disables WYSIWYG resynthesis for parts of your design.

Note: Primitive node names are specified during synthesis. When netlist optimizations are applied, node names might change because primitives are created and removed. HDL attributes applied to preserve logic in third-party synthesis tools cannot be maintained because those attributes are not written into the atom netlist, which the Intel® Quartus® Prime software reads.

If you use the Intel® Quartus® Prime software to synthesize your design, you can use the Preserve Register (preserve) and Keep Combinational Logic (keep) attributes to maintain certain nodes in the design.

Figure 51.  Intel® Quartus® Prime Flow for WYSIWYG Primitive Resynthesis

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